The present invention relates, in general, to multipliers and, more particularly, to a cryptographic multiplier.
Rivest-Shamir-Adleman (RSA) is a widely used cryptographic algorithm that provides high security for digital data transfers between electronic devices. The modular exponentiation mathematics of the RSA algorithm can be efficiently computed using Montgomery""s method for modular reduction based on a hardware multiplier. Modular exponentiation of large integers can be efficiently computed with repeated modular multiplications and the efficiency of the overall RSA computation is directly related to the speed of the multiplier. Hardware multiplier architectures use pipelining techniques for the massive parallel computations of the Montgomery algorithm. A pipelined hardware multiplier computing the Montgomery algorithm can provide speed and silicon area tradeoffs that provide both a high performance and a cost effective solution. In addition, the pipelined integer modular multiplier offers lower power which is required for many applications.
The cryptosystem facilitated by the RSA algorithm offers a high level of security but is expensive to implement. Although the mathematics of the RSA algorithm with modular exponentiation are straight forward, efficient hardware implementation is not straight forward. With increasing demand for faster cryptographic operations and higher performance, hardware modular multiplier architecture improvements are needed to ensure high levels of security.
Accordingly, it would be advantageous to have a modular exponentiation and multiplication system that achieves high performance, low cost, and low-power for implementation in an integrated circuit. A need exists for a multiplication system that achieves high performance by computing the Montgomery algorithm in fewer clock cycles than in prior art systems. A further need exists for a multiplication system that is adaptable to operands having an increased number of bits.